The present invention relates to dynamic logic circuits, and in particular, to dynamic logic circuits having a dynamic switching factor to reduce power consumption.
Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically, by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their xe2x80x9csteady-statexe2x80x9d values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock each cycle may consume power even when the logical value of the output is otherwise unchanged.
This may be appreciated by referring to FIG. 1.1 illustrating an exemplary three-input OR dynamic logic gate, and the accompanying timing diagram, FIG. 1.2. Dynamic logic 100, FIG. 1.1, includes three inputs a, b and c coupled to a corresponding gate of NFETs 102a-102c. During an evaluate phase of clock 104, N1, NFET 106 is active, and if any of inputs a, b or c are active, dynamic node 108 is pulled low, and the output OUT goes xe2x80x9chighxe2x80x9d via inverter 110. Thus, referring to FIG. 1.2, which is illustrative, at t1 input a goes high during a precharge phase N2 of clock 104. During the precharge phase N2 of clock 104, dynamic node 108 is precharged via PFET 112. Half-latch PFET 114 maintains the charge on dynamic node 108 through the evaluate phase, unless one or more of inputs a, b or c is asserted. In the illustrative timing diagrams in FIG. 1.2, input a is xe2x80x9chighxe2x80x9d having a time interval t1, through t2 that spans approximately 2xc2xd cycles of clock 104, which includes evaluation phases, 116 and 118. Consequently, dynamic node 108 undergoes two discharge-precharge cycles, 124 and 126. The output node similarly undergoes two discharge-precharge cycles, albeit with opposite phase, 124 and 126. Because the output is discharged during the precharge phase of dynamic node 108, even though the Boolean value of the logical function is xe2x80x9ctruexe2x80x9d (that is, xe2x80x9chighxe2x80x9d in the embodiment of OR gate 100) the dynamic logic dissipates power even when the input signal states are unchanged.
Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments.
Limited switching dynamic logic (LSDL) circuits produce circuits which mitigate the dynamic switching factor of dynamic logic gates with the addition of static logic devices which serve to isolate the dynamic node from the output node. Co-pending U.S. Patent Application entitled, xe2x80x9cCIRCUITS AND SYSTEMS FOR LIMITED SWITCH DYNAMIC LOGIC,xe2x80x9d Ser. No. 10/116,612 filed Apr. 4, 2002 and commonly owned, recites such circuits. Additionally, LSDL circuits and systems maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement. However, the logic tree that is the heart of dynamic logic and in particular LSDL circuits have a limit to the fan-in for the logic function. Therefore, there is a need for LSDL circuits that allow a larger fan-in for logic functions. In standard LSDL circuits, the static logic devices which serve to isolate the dynamic node perform only an inverting function between its input and output. Therefore, there is a need for the static logic devices in LSDL to form more complex logic functions while maintaining the advantages of a standard LSDL circuit.
The aforementioned needs are addressed by the present invention. Accordingly, there is a limited switch dynamic logic (LSDL) circuit configuration with a plurality of dynamic logic circuits each having a corresponding dynamic node, and a plurality of logic input signals, wherein each dynamic node has a precharge value during a first phase of a clock signal and an asserted value corresponding to a Boolean combination of its corresponding plurality of input signals during the second phase of the clock signal. The plurality of dynamic nodes are further coupled to a static logic section which further generates an output and complement output of the LSDL circuit that is the value corresponding to a final Boolean combination of the asserted values of the dynamic logic gates. The static logic section is configured to combine the outputs of the plurality of dynamic logic gates performing the final Boolean function on logic values of the dynamic nodes during the first phase of the clock signal and holding the value of the final Boolean function during the second phase of the clock signal.
Additionally, there are provided logic systems and circuits including a plurality of LSDL circuits for asserting Boolean functions of a plurality of input signals, in which a signal on a first node asserted in response to a first phase of a clock signal constitutes a plurality of Boolean combinations of the plurality of input signals. Also included is a static portion coupled to the first node. The static portion is configured to combine the outputs of the dynamic logic portions while maintaining an output value of the logic device during a second phase of the clock signal; the output value represents a total Boolean function performed by the dynamic portions and the static portion. Also, a duration of the first phase of the clock signal is less than a duration of the second phase of the clock signal.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.